1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a phase-change memory device having a bottom electrode contact and a method of manufacturing the same.
2. Related Art
Today's portable information communication systems are capable of processing large-scale information through a wireless scheme. Such systems require memory devices having high-speed and mass-storage capabilities. Such a memory device must have a non-volatile function of a normal flash memory device, high-speed performance of an SRAM (static random access memory), and a high-integration function of a DRAM (dynamic RAM) while reducing power consumption thereof. An FRAM (ferroelectric RAM), an MRAM (magnetic RAM), a PRAM (phase-change RAM), and an NFGM (nano floating gate memory), which represent superior characteristics in terms of power consumption, data retention and write/read performance as compared with the normal memory device, have been proposed to meet these needs.
Among other things, a PRAM has a simple structure and can be fabricated at a low cost. In addition, the PRAM can be operated at a high-speed, which makes PRAM technology a potentially good option for meeting the needs of today's, and tomorrow's portable systems.
A conventional PRAM has a phase change layer, in which a crystal phase of the phase change layer is changed according to heat generated from a current applied thereto. A chalcogenide compound (Ge—Sb—Te; GST) composed of germanium (Ge), antimony (Sb), and tellurium (Te) is often used as a phase change layer for the PRAM. The phase of the phase change layer, such as a GST, may be changed based on heat generated in the phase change layer due to current flowing through the phase change layer.
A GST, for example, has high resistivity when it is in an amorphous state and a low resistivity when it is in a crystal state. Therefore, the states of the GST can be used to indicate different logic values, and thus the GST can be used as a data storage medium of a memory device.
A phase change memory device should have low power consumption and high integration characteristics, so various attempts have been made to reduce the operational current of conventional GST, i.e., to reduce the reset current of the GST.
A method of reducing a contact area between a GST layer and a bottom electrode contact is extensively used to reduce the reset current. In order to reduce the contact area between the GST layer and the bottom electrode contact, the bottom electrode contact is fabricated through a lithography process such that the bottom electrode contact has a minimum diameter. However, although the reset current can be improved due to reduction of the contact area between the bottom electrode contact and the GST layer, a contact area between the bottom electrode contact and a switching device, which is provided at a lower portion of the bottom electrode contact, will also be reduced. For this reason, contact resistance between the bottom electrode contact and the switching device may increase, so that on current is lowered.